//
//					16-bit Adjustable-length Shift register
//
//					(C) Copyright 2004 John B. Stephensen
//
// This Verilog source file and all its derivatives are licensed only for
// personal non-profit educational use in the Amateur Radio Service and
// the license is not transferrable. The information is provided as-is for
// experimental purposes and the author does not warranty its freedom
// from defects or its suitability for any specific application.
//
//	1 slice.
//
module srl16x1e(y,d,a,ce,clk);
    output y;			// output selected by address
    input d;			// input
	 input [3:0] a;	// address of output word
    input ce;			// enable input
    input clk;			// clock input
// 32-bit shift register
SRLC16E sr (.D(d), .A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]), .Q(y), .Q15(), .CLK(clk), .CE(ce));
endmodule
